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Abstract This thesisisdividedintofivechaptersasfollows: Chapter 1 givesanintroductiontothefrequencysynthesizersandclockmul- tipliers applicationssuchaswirelessandwirelinetransceivers.Thenitpresents the performancechallengeswhichfacetheconventionalfrequencysynthesizers. Finally,itshowsthemotivationofthisthesisfollowedbythethesisorganiza- tion. Chapter 2 providesaliteraturesurveyforhigh-performanceclockmultipliers suchasmultiplyingdelay-lockedloopsandinjection-lockedoscillators.Thena detailed surveyforinjection-lockedoscillatorsandtheirfrequencycalibrators is presented. Chapter 3 showsthesystemdesignandthenoiseanalysisfortheproposed injection-lockedclockmultiplier.Thenitdiscussesthedesignofinjection- lockedoscillatoranditspredictedlockingrange.Finally,thedesignofthe frequency-trackingloopanditsbuildingblocksaredemonstratedindetails followedbythesimulationresultsandperformancecomparisonwiththestate of artdesigns. ix Chapter 4 depicts theproposedreferencefrequencyquadruplerwithduty cycle correctionlooptobeintegratedwiththeinjection-lockedclockmulti- plier. Thentheachievedresultsarecomparedwiththestateofartfrequency quadruplers. Chapter 5 concludes andsummarizestheworkpresentedinthisthesisas wellasproposessuggestionsforthefutureworktofurtheroptimizetheper- formance. |