الفهرس 
INTRODUCTIONOnly 14 pages are availabe for public view
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Abstract
This dissertation demonstrates Integrated-Circuits yield enhancement mechanisms with a focus on LEPB as a well-known systematic defect in BEOL layers. The dissertation firstly introduces GPS, then employs GPS features to model LEPB using supervised regression-based ML regressors and perform IC layout topological profiling. The dissertation is in five chapters organized as follows:
Chapter One: This chapter introduces systematic yield loss in advanced IC manufacturing processes with focus on LEPB as one of the well know systematic defects in BEOL interconnect layers that significantly affect the IC yield. It begins with the motivation of this thesis, then reviews the scope and the main contributions. Finally, it ends with an overview of the organization of this thesis.
Chapter Two: This chapter provides an overview of ML employment in IC layout-based applications, either during the IC design phase or the IC manufacturing phase, focusing on applications that use features derived from IC layouts. Afterward, it reviews common ML modeling approaches for IC layouts-based applications. Then, it reviews common IC layout representations for ML applications and states the drawbacks of these representations. Finally, it concludes the need for a new approach for IC layout pattern features representation that can be used directly with predefined architected off-the-shelf ML models.
Chapter Three: This chapter explains GPS in detail. It starts by highlighting the constrained generality in IC layouts. Then, it reviews the essence of the GPS and its measurements contractors. These constructors use core geometrical measuring functions that eventually produce GPS features vector. Afterwards, it demonstrates the decomposition of GPS features into topological and dimensional features. Then, it describes the implementation of GPS engine and its layered architecture. Thereafter, it shows the adaptability of GPS features to ML modeling domain and points to IC topological profiling using GPS topological features. Eventually, it quantifies the performance of GPS in terms of run time and peak memory consumption.
Chapter Four: This chapter targets LEPB modeling using GPS features through regression based supervised learning ML approaches. It starts with reviewing LEPB modeling aspects from lithographic point of view, then it demonstrates the employed manufacturing flow for simulations and data harvesting, including GPS features, density grid pixels features, and density CCAS features. Afterward, it explains the ML modeling flow and the deigned experimental evaluations. Finally, it reviews the obtained modeling results and the efficiency of the used representations.
Chapter Five: This chapter introduces an automated IC layout patterns topological profiling approach using GPS features. It starts with reviewing the current approaches of IC layout patterns profiling. Then, it explains the topological clustering based on GPS topological features. This makes the patterns topological profiling doesn’t need complex models and can be controlled to produce adequate patterns profiling granularity that is not easily approached by other patterns profiling alternatives. Afterwards, it proposes two potential applications for the proposed topological clustering. The first application is LEPB profiling within the parent topological clusters, and the second application is to identify the dimensional differences between DFM-HS and DFM-NHS within the same topological cluster.
Eventually, the thesis is concluded by discussing the obtained results, highlighting the findings, and suggesting the future work that can be built on this thesis.