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العنوان
A Specialized Hardware for High-Performance Computational Storage /
المؤلف
Fakhry, Dina Walid Mohamed.
هيئة الاعداد
باحث / دينا وليد محمد فخري
مشرف / محمد واثق علي كامل الخراشي
مشرف / مني محمد حسن صفر
مشرف / محمد عبد السلام أحمد حسن
تاريخ النشر
2023.
عدد الصفحات
109 p. :
اللغة
الإنجليزية
الدرجة
ماجستير
التخصص
Computer Science (miscellaneous)
تاريخ الإجازة
1/1/2023
مكان الإجازة
جامعة عين شمس - كلية الهندسة - هندسة الحاسبات والنظم
الفهرس
Only 14 pages are availabe for public view

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Abstract

Transferring data to CPUs for computation has imposed notable bottlenecks especially for applications with limited data reuse. Allowing processing close to where the data resides can tremendously help surpass such bottlenecks. It also allows mitigating data movement problems generated by data-intensive applications leading to enhancements that range from energy efficiency to bandwidth allocation.
In this research, we survey previous proposals of Near Data Processing (NDP) both near memory and near storage both. We discuss key challenges and suggest future research directions. We investigate augmenting the High Bandwidth Memory 3 (HBM3) memory controller with compute units to address data integrity and security and analyze different design aspects including area and power.
The thesis is divided into five chapters as listed below:
Chapter 1 provides an introduction and an overview on NDP focusing on the different classifications available. It outlines the organization of the thesis and lists the main objectives and contributions.
Chapter 2 summarizes some notable related works in the literature both for In Storage Computing (ISC) and In Memory Computing (IMC). It provides an overview on systematization and outlines the metrics needed to allow for NDP-Friendly Applications.
Chapter 3 discusses challenges related to NDP that include cache coherency, virtual memory support, programming models, security and filesystems. It also provides an overview on the different interfaces available that can be keys to achieving the best out of ISC and IMC.
Chapter 4 provides an overview on Dynamic Random Access Memory (DRAM) architecture and their applications and propose the inclusion of computation units, mainly Cyclic Redundancy Check (CRC) and Advanced Encryption Standard (AES), for PIM within HBM3 memory controller. We evaluate the experimental design and discuss enhancements gained with respect to area and power consumption.
Chapter 5 concludes the thesis highlighting the thesis’s contribution and providing proposals to some future work directions that may benefit this research area.