الفهرس 
Chapter 1 IntroductionOnly 14 pages are availabe for public view
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Abstract
This thesis aims to study the analysis of the dynamics of Bang-Bang Phase Locked Loops (BBPLLs) and Time to Digital Converter all-digital Phase Locked Loops (TDC ADPLLs), which are the two main architectures of all-digital Phase Locked Loops (AD- PLLs) that have been widely used to realize low jitter PLLs. Moreover, this thesis aims to study the design of the control loops used for optimizing the dynamics of BBPLLs and TDC ADPLLs.
Furthermore, this thesis provides a literature survey on the analysis of the dynamics of BBPLLs and TDC ADPLLs. Moreover, this thesis provides a literature survey on the control loops proposed for automatically optimizing the dynamics of BBPLLs and TDC ADPLLs. The dynamics of BBPLLs are optimized by optimizing the value of the Digital Loop Filter (DLF) proportional gain (β), while the dynamics of TDC ADPLLs are optimized by optimizing the values of both the DLF proportional gain (β) and the TDC resolution (Tres).
Furthermore, this thesis proposes two control loops for automatically optimizing the dynamics of TDC ADPLLs. The first control loop is used for optimizing the TDC res- olution (Tres). This proposed resolution control loop minimizes the TDC resolution until the TDC linear dynamic range equals the range of the input time error. Conse- quently, PLL in-band phase noise is reduced due to reduction of the Power Spectral Density (PSD) of the TDC quantization noise. Moreover, the linearity of the TDC transfer function across the range of the input time error is guaranteed. Furthermore, the second control loop is used for optimizing both the DLF proportional gain (β) and the TDC resolution (Tres) using jitter monitoring. This proposed control loop sweeps the DLF proportional gain (β) and the TDC resolution (Tres) and then chooses the optimum settings for the DLF proportional gain (β) and the TDC resolution (Tres) at which the local minimum of the PLL jitter is achieved.