الفهرس 
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Abstract
The Thesis ‘Real Number Modelling of Phase Locked Loop Circuits’ presents the system level design using MATLAB and High-level abstraction design using SystemVerilog-Real Number Modelling (SV-RNM) Hardware Description Language (HDL). Moreover, the verification of Phase Locked Loop (PLL) using Constraint Randomized Verification (CRV), Functional Coverage, Assertions, Checkers, and Universal Verification Methodology (UVM). Finally, Validate the PLL system by putting the system in a full Analog-Mixed System.
The thesis is divided into six chapters and two appendices with the lists of contents, tables, figures, and abbreviations as well as the list of references.
Chapter 1: The chapter discusses the need for high level abstraction for analog circuits. Then the research focus and thesis contributions are demonstrated.
Chapter 2: The chapter provides literature survey on the RNM constructs that could be used during modelling analog blocks using SV-RNM and a few analog modelled blocks using these RNM constructs. An intro for modelling PLL as it’s an essential block for all chips.
Chapter 3: The chapter demonstrates the system level design of different specifications and requirement of PLLs therefore, two systems are introduced to show the tradeoff between decreasing phase noise (decrease jitter) and fast locking of the PLL. The chapter covers ensuring the stability of the loop, locking of the loop, and phase noise analysis then converts PN to RMS jitter.
Chapter 4: The chapter introduces the PLL modelling using SystemVerilog-Real Number Modelling (SV-RNM) and new techniques are provided to increase accuracy. The PWL technique could model filters within a feedback loop. The resolved nets when driving multiple drivers as driving multiple loads through the same net. Modelling the value of s-domain signals by using class datatype.
Chapter 5: The chapter highlights different verification techniques for analog modelled DUTs in digital environment using Randomization of real data, assertion on functionality, and Functional coverage of real signals. Finally, UVM-based verification for these analog DUTs (as PLLs) and a UVM environment for PLL integrated with pure RTL design and with another analog model DUTs.
Chapter 6: The chapter summarizes the work done in the thesis, and illustrates the future work that can be done on an analog circuit validation as a transistor level.
Appendix A: The Appendix contains the MATLAB codes responsible for ensuring the stability of the second and third order PLL. Moreover, the codes for Phase Noise (PN) model and a code for converting PN to RMS Jitter.
Appendix B: The Appendix provides the Verilog-A codes for ensuring the PLL locking.
Key words: PLL, Phase Noise (PN), Jitter, SV-RNM, UVM.