الفهرس 
IntroductionOnly 14 pages are availabe for public view
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Abstract
Research and improvement of future generation wireless communication technologies operating on higher frequency bands is growing vastly, creating a need for high performance transceivers tailored to the particular specifications of these bands. Communications using Ultra-Wide Band (UWB) technology become attractive due to the wide available frequency range between 3.1GHz to 10.6 GHz, which is a potential candidate for many new applications such as 5G mobile communication systems and Wireless Vehicular radar systems. This thesis presents a new method for Ultra Wideband power Amplifier Design. Two different UWB PA configurations will be investigated. Excellent specifications of the designed UWB PA were achieved.
The first proposed design provided a two-stage cascaded power amplifier (PA) employing a proposed Resistor-Capacitor (RC) interstage. The current-reuse topology is employed at the first stage to lower the power consumption, while the RC interstage helps to enrich the gain flatness and the wideband matching. The shunt peaking topology in a common source configuration is adopted at the second stage to enhance the power gain. The postlayout simulation is performed using the TSMC 65 nm CMOS process operating in a frequency band of 3.1 GHz to 10.6 GHz. The postlayout simulation results indicate that a high flat gain of approximately 22.8 ± 1.2 dB, small group delay variation of ±50 ps, and good input and output matching of less than -10 dB are achieved over the desired working band. Moreover, a saturated output power of 10 dBm and maximum power-added efficiency (PAE) of 29.5% is achieved at 6 GHz. The proposed PA consumes the low power of 15.5mW from 1.2 V supply voltage.
The second proposed design offers a highly efficient (3.1 -10.6) GHz ultra wide band (UWB) power amplifier (PA) with an improvement in the input matching, using the process of CMOS TSMC 0.065 µm. A wide input matching topology and a resistor-capacitor (RC) interstage are adopted for input matching and flatten gain improvements, respectively. The feedback circuit leading the gate inductor combined with the peaking inductive divider accomplishes a low input return loss and extends the band of operation. The post-layout simulations indicate a high flattened average power gain (S21) of 22.2 ± 1.5 dB while the improved matching topology attains a good input (S11) and output (S22) return loss below -11 dB. Moreover, a small group delay (GD) variation of ± 47.5 ps is achieved for the UWB frequencies. In addition, a great power-added efficiency (PAE) of 33% and an output power (P_out) of 11 dBm are achieved. The complete UWB PA design consumes only 19 mW from 1.2 supply voltage.