الفهرس 
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Abstract
In this thesis we investigate the idea of using the Machine learning algorithm, Reinforcement Learning (RL) in the scheduling of Memory Controllers. This idea was first introduced as the state-of-art Self-Optimizing Memory Control-lers. Self-Optimizing Memory Controllers present great potential in the Chip Multiprocessing systems where different cores share the same memory system with varying memory access patterned requests. As they provide adaptable memory scheduling that can tune its scheduling biases based on the optimiza-tion goal set by the designer.
In this work we study the current Self-Optimizing Memory architectures pro-posed, present their possible setbacks, and suggest design improvements ac-cordingly. We propose scheduling references on the DRAM request-level and proposed adding an extra system attribute to account for the contention of the per-bank FIFOs.
We implemented our design in gem5 open-source processor simulator and used PARSEC benchmark suite to evaluate the performance.
The thesis is divided into seven chapters as listed below:
Chapter 1: In this chapter we give a brief introduction to the background and motivation of this work, the research objectives and a roadmap for the thesis.
Chapter 2: In this chapter we provide a background on memory systems, spe-cifically DDR DRAMs. We present their architecture, memory timing con-straints and the responsibilities of a DDR memory controller.
Chapter 3: In this chapter we discuss related work. We first present the conven-tional state-of-art memory scheduling techniques. We then discuss the work done on Self-Optimizing memory controllers and where possible setbacks lie.
Chapter 4: In this chapter we explain Reinforcement Learning Algorithm. Its environment setup, reward structure and different control methods. We also touch upon the role of function approximators in Reinforcement Learning set-ups.
Chapter 5: In this chapter we present our RL-based Memory controller. We de-scribe in detail the architectural design, the RL algorithm implemented and the block diagram of the controller.
Chapter 6: In this chapter we discuss the experimental setup that was used to evaluate the design and the results achieved.
Chapter 7: In this chapter we conclude the work done in the thesis and present ideas for future work. We also list our contributions in Self-Optimizing Memory Controllers.
Keywords: Machine Learning, Memory Controllers, DRAM, Reinforcement Learning.