الفهرس 
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Abstract
This thesis aims to study the design of low-power output-compensated low drop-out regulators (LDOs) with improved power supply rejection (PSR) and inrush current. The thesis is divided into two main parts, first one is for designing an ultra-low-power high PSR LDO using adaptive loop gain control. And second one is for designing a low-power, improved inrush current, wide-load range and high PSR LDO using feed-forward load-dependent cancellation buffer (FFLCB) and pass device splitting.
One of the most critical parameters of the LDOs is its PSR over different frequencies. In this thesis we propose two different designs for a high PSR LDO.
The first one is a low-power LDO with two methods of high-frequency PSR and loop stability compensation techniques. The proposed LDO achieves a high PSR over a wide frequency range with low power and small area consumption. The LDO is implemented in 65-nm CMOS technology and achieves a PSR better than 77 dB up to 30 MHz for output load currents up to 25 mA and a 4-µF output load capacitor. The design is suitable for output compensated (Capped) LDOs with a wide output load current range up to 100 mA and output load capacitor range from 1 µF to 12 µF. The proposed LDO consumes a quiescent current of 5 µA and an area of 400 µm x 200 µm.
The second proposed design is a low-power LDO with two PSR compensation techniques. One using a FFLCB technique. And another one based on improving the LDO loop gain across high frequencies. The proposed LDO achieves a high PSR over a wide frequency range with low power and area consumption. The LDO is implemented in 65 nm CMOS technology and achieves a PSR better than 80 dB up to 30 MHz for output load currents up to 25 mA with a 4-µF output load cap. The design is suitable for capped LDOs with wide load current ranges from 0 to 200 mA and load capacitor range from 1 nF to 12 µF with inrush current improvement by more than 2X. The proposed LDO consumes a no-load quiescent current of 10 µA and an area of 200 µm x 180 µm.