الفهرس 
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Abstract
onvolutional encoder and Viterbi decoder on a field programmable gate array (FPGA) board is so demanding.
This thesis describes the design and implementation of inner convolutional encoder and a soft Viterbi decoder with inner interleaver/de-interleaver of standard DVB-T system (that are essential blocks in digital communication systems) with a constrained length of 7 and a code rate of 2/3, using Xilinx ISE (Integrated Software Environment) design suite 12.4 and comparing their results with that of the IPcore built-in design on Xilinx ISE design Suite 12.4 program.
The designed channel convolutional encoder and Viterbi decoder follow European Standard ETSI EN 300 744 for digital terrestrial television. Verification of the design is accomplished by loopback and by comparison with the corresponding Xilinx core. Utilization and timing reports of implemented device on Vertex 6 are included.
Key words:
Channel Coding; Convolutional Coding (Inner Coding); DVB-T; Inner Interleaver; Inner deinterleaver; Viterbi decoder.