الفهرس 
Frequency Synthesizers ApplicationsOnly 14 pages are availabe for public view
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Abstract
Highly digital clock generator architectures, commonly imple-
mented using digital phase-locked loops (DPLLs), are evolving
as the preferred means for synthesizing high frequency on-chip
clocks. By obviating the need for a large loop lter capacitor and
high performance charge-pump, DPLLs offer many advantages
over classical charge-pump PLLs. Their main bene ts include
small area, reduced sensitivity to analog circuit imperfections,
immunity to process, voltage, and temperature (PVT) variations,and easier scalability to newer processes. Recently, Digital Mul-
tiplying Delay Locked Loop (DMDLL) showed superior perfor-
mance over the DPLLs for the same building blocks. Unfortu-
nately, DMDLL is still limited to Integer multiplication only of
the reference frequency which limits its elds of application. To
overcome this drawback of DMDLLs, this thesis introduces two
possible solutions.
The rst one is by using the regular integer DMDLL followed
by a set of open loop fractional dividers. The proposed open
loop fractional divider is used to eliminate the deterministic jitter
caused by the conventional fractional dividers without additional
calibration. The proposed divider utilizes a new voltage com-
parator based Digital-to-Time converter (DTC) as an adjustable
delay circuit to control the edges of the output clock of the di-
vider. The proposed DTC proves to be power efficient consider-
ing its resolution and the frequency of the output clock. Detailed
analysis of non-idealities of the proposed architecture and its ef-
fect on the cancellation of the deterministic jitter are presented
and veri ed by simulations. Simulation results show that for an
input frequency of 5.325 GHz and output frequency of 1 GHz,
the proposed divider achieves a 0.2 ps of time resolution using a
10-bits DTC while consuming 3.72 mW and 1.17 mW from 1.2 V
and 0.9 V supply,for 130 nm and 65 nm CMOS technology nodes,
respectively.
The second solution is by proposing a new calibration free
Fractional Digital MDLL (FDMDLL) clock multiplier where the integer DMDLL itself is converted into fractional one. The new
fractional MDLL relies on using a digital-to-time converter (DTC)
to align the edge of the reference clock to the oscillator output
clock. Moreover, a power efficient frequency locked loop (FLL)
is proposed as a part of FDMDLL. The proposed architecture is
simulated using 130 nm CMOS technology node. The output fre-
quency ranges from 2-3 GHz from a 64 MHz reference frequency,
The simulated integrated rms jitter is 0.77 ps at an output fre-
quency of 2.4 GHz. The FDMDLL consumes 2 mW from a 1.2
V supply, and has an effective area of 0.21 mm2.