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العنوان
Nanometer Layout Effects on Analog Front
End Circuit Design
المؤلف
Elshawy, Mohannad Elemam.
هيئة الاعداد
باحث / Mohannad Elemam Elshawy
مشرف / Mohamed Amin Dessouky
مشرف / Mohamed Ahmed Elsheikh Mohamed
مناقش / Mohamed AbdElhamid Abo El-Atta
تاريخ النشر
2015.
عدد الصفحات
105p. :
اللغة
الإنجليزية
الدرجة
ماجستير
التخصص
الهندسة (متفرقات)
تاريخ الإجازة
1/1/2015
مكان الإجازة
جامعة عين شمس - كلية الهندسة - Communication Engineering
الفهرس
Only 14 pages are availabe for public view

from 105

from 105

Abstract

ABSTRACT
During the past few years, the concept of integrating multiple applica- tions into a single System-on-Chip (SOC) has occupied a huge segment in the market of integrated circuits. The recent development in this area has led to an increase in the number of Analog/Mixed signal (AMS) com- ponents and the functionality that can be integrated per chip. In the digital design flow, the design procedure is captured and the level of automation has been performed easily. On the other counterpart, the AMS design flow suffers from a lack of automation and requires a manual interaction from designer throughout all the design process. Moreover, the design chal- lenges in the advanced nodes beyond 90 nm becomes more significant and tedious for any analog designer. It would be desirable to automate part of the analog design flow (back-end phase) using layout generators to minimize the gap between the front end and back end phases as the layout dependent effects (LDEs) become more significant and tedious for the analog designer in the recent nanometer technology beyond 90 nm.
This work addresses a new analog design methodology that mitigates layout dependent effects (LDEs) on analog circuits. The proposed method- ology offers a solution for these effects by minimizing the gap between the electrical and physical design. A layout generator tool is developed and used within the proposed flow. The layout generator tool is param- eterized to generate the layout of basic analog building blocks such as Differential Pair and Current Mirror circuits after sizing these circuits in the front end phase by circuit designer. In order to validate the impor- tance of the proposed design methodology, a two stage Miller OTA and a current steering digital to analog converted (DAC) are designed using the
proposed methodology and presented as a case study. All the circuits are designed in 28nm technology and the LDE extraction is done by Calibre- LVS tool to guarantee the accuracy of the extracted data. The developed layout generator tool is used in the design process in order to show the main usage of this tool within the proposed design methodology.
Keywords: Analog Layout Synthesis, Layout Generation, Analog Design, Layout Dependent Effects, CA