الفهرس 
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Abstract
Ahmed Mamdouh Badawy, Design of Analog to Digital Converters in Nanometer Technology, master of Science dissertation, Ain Shams University, 2014.
In recent years the demand for low voltage, low power and high speed analog to digital converters has significantly increased. In modern technologies the devices feature length has decreased increasing the ability to implement more circuits on the same die area. However, the primary limiting factor is the power consumption of such extra circuitry. Therefore, the objective of this work is to design and build a power efficient solution for medium resolution Analog to Digital Converters (ADC).
As a proof of concept, a low power 5-bit Binary Search ADC (BSADC) is designed in 65nm CMOS technology to enhance the ADC throughput without increasing the analog circuits complexity. The presented technique is able to increase the output throughput to Fsample using a new sample and hold combination. This ADC works under a low supply voltage of 0.8V and can achieve sampling rates up to 1GS/s with a low Figure of Merit (FOM) of 50fJ/conversion-step.
A high resolution 10-bit Pipeline ADC is also designed using the same technology. This high resolution ADC uses the previously designed BSADC as a SUB-ADC in the last stage. This ADC is completely designed to achieve high performance at 1.3V supply and 100MS/s.
Key words: ADC, Binary Search, High Speed, Low Voltage, Pipelined ADC
SUMMARY
This dissertation demonstrates a technique for conversion speed enhancement of the Binary Search Analog to Digital Converters and then using this converter as a final stage in a pipeline ADC. The dissertation is divided into five chapters organized as follows:
Chapter One: This chapter presents motivation to the work presented in this thesis and our contribution.
Chapter Two: This chapter is an introduction to Analog to Digital Converters basics, performance parameters and describes state of the art.
Chapter Three: This chapter presents the system level architecture of the proposed BSADC and pipeline ADC. Behavioral model results are presented.
Chapter Four: In this chapter, a 5-bit Binary Search Analog to Digital Converter is designed. The main blocks are analyzed, designed, and simulated. Results are presented and compared to similar work of some other authors.
Chapter Five: In this chapter, a 10-bit, 100-MS/s pipeline ADC is designed using the BSADC as a sub-adc in the last stage. The main blocks are analyzed, designed, and simulated.
Finally, the thesis ends by extracting conclusions and stating future work that might be done based on this work.