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Today’s consumers demand wireless systems that are low-cost, power efficient, reliable and have a high integration form. High levels of integration are desired to
reduce cost and achieve compact form. Hence the long term vision of goal for
wireless transceiver is to merge as many components as possible to a single die in an inexpensive technology. Therefore, there is a growing interest in utilizing CMOS technologies for RF power amplifiers (PAs). Although several advances have been made recently to enable full integration of PAs into CMOS technology, it is still among the most difficult challenges in achieving a truly single-chip
CMOS radio system.
The total integration of RF building blocks can lower the cost and chip area,
which makes the Si-based design a better choose than the multiple-dies,
based design. Additionally, advancements in CMOS technology for integrated power amplifier in the gigahertz range have been reported. It has shown that, with improved techniques, CMOS can become a prospected candidate for RF PA design.
Efficiency enhancement of RF power amplifiers is crucial for modern wireless communication systems. Many techniques have been developed for efficiency enhancement in power amplifier design. Furthermore, linearity improvement
technique using the cancellation of nonlinear terms is proposed for the CMOS
power amplifier in combination with the efficiency enhancement technique. Also,
power amplifier must be designed to be able to control the dc consumption to
improve the overall efficiency.