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العنوان
Design and realization of an electrically programmable cmos mempry cell ( EEPROM ) based on the hci into the floating gate
الناشر
Electronics and computer engineering dpt.
المؤلف
EL-Hennawy, Samy Ezzat Mohamed .
هيئة الاعداد
باحث / سامى عزت محمد الحناوى
مشرف / محمد نبيل صالح
مشرف / احمد الحناوى
مناقش / A.A. Talkhan
مناقش / A. Kh. Abo-El Seoud
الموضوع
MOS memory
تاريخ النشر
1988
عدد الصفحات
106 p.
اللغة
الإنجليزية
الدرجة
ماجستير
التخصص
الهندسة الكهربائية والالكترونية
تاريخ الإجازة
1/1/1988
مكان الإجازة
جامعة عين شمس - كلية الهندسة - الكترونات و اتصالات
الفهرس
Only 14 pages are availabe for public view

from 120

from 120

Abstract

It is the purpose of this thesis to give a detailed
study and analysis of a new non-volatlle CMOS EEPROM memory
cell. It is based on a non destructive mechanism of carrier
lieating and injection into the gate oxide. It employs a
double-gate CMOS inverter. Tl1is or-Iei na i cell Is faster,
much more rel1able and slmpler than all generatlons which
nave already been rea 11zed. Circuit design
allows
programming and erasing w i t.n a si ns i e supply voltage of 5V
(crianneI length L ~ 2 IJm).
The clrcult latches the Input
data owing to the bidirectional hot carrier gate current.
In chapter 1 the thesls presents a survey of the
d1fferent types and generations of the memory cells. It
studies the
effects of the new technologles on the
performance and characteristics of these cells.
Study and characterization of this CMOS EEPROM requires
a good Knowledge of the carrler heatlng phenomena, the hot
carrler gate current and the effects of scaling-down on the
MOSFET parameters and the performance and characterlstlcs of
the memory cell. We nav e al so to reveal the ef f ect s of voltage and temperature stress1ng on the memory performance
and characterlstlcs through a detailed reliabillty study 2
We introduce in chapter 2 a simulat10n techn1que to
compute the output voltage Vo(t) of the memory cell during
programming and erasing cycles and also the programming time
tp. We propose also two analytical models,
one for the
evaluation of the threshold voltage shift and the other to
predict the mobil1ty degradation aSSOCiated w1th device
scal ing-down.
In chapter 2 we also develop a new monochannel MOS
EEPROM wh1ch acq\lires the
CMOS EEPROM and, at the
main advantages of the presented
same t1me,
1s free from the
drawbacks of the CMOS technolgy used 1n fabricating the
presented EEPROM.
In chapter 3 we present the experimental and simulation
results. We d1scuss these results and summarize the main
features of the new CMOS EEPROM we presented.
In chapter 4 the thes1s presents conclusions of the
present study and proposes new po1nts for the future
research.