الفهرس يوجد فقط 14 صفحة متاحة للعرض العام
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المستخلص
Breaking over 100 M bits’s data throughput barrier of FDDI or Fast Ethernet pushes ATM to be the most efficient solution. On the other hand. ATM integrated circuits are targeted to address mono-rate transmission. Therefore, when a network performance upgrade is needed, one has to change hardware with cost and traffic interruption. A re-configurable and re-programmable ATM line terminator is the possible and easy solution.
This requirement can be achieved by using Field Programmable Gate Array (FPGA) as it offers more flexibility during the design cycle as
well as after finishing the implementation In this thesis, a cell-based transmission convergence sublayer is proposed for the ATM line terminator.
The design is simulated using Mentor Graphics FPGA - Advantage toll version 5.5 tool. The performance behavior of the design has been taken. Also the implementation file obtained from Xilinix ISE version 6.21 tool.
Finally, the optimized design is presented with the performance evaluation.