الفهرس 
INTRODUCTIONOnly 14 pages are availabe for public view
 |  | from | 173 |  |  |
| | | from | 173 | | |
Abstract
As the semiconductor technology scales down to the deep submicron domain, integrated circuit (IC) yield becomes more sensitive to various high-order effects, which impacts manufacturing cost and chip reliability. Systematic defects emerge, in which layout pattern configurations become more sensitive to the manufacturing process, frequently resulting in defective circuit components, and causing electrical behavioral malfunction. These systematic defects are one of the main contributors to IC yield loss. Shrinkage in manufactured device dimensions and pattern densities turn the identification of systematic defect patterns in the back end of line (BEOL) interconnect layers into a challenging process with more geo-contextually dependence than ever before, limited not only to the defect’s planar layer domain but also across multiple layers in the stack. This challenge imposes more sophisticated design rules checks (DRC) defined by the IC manufacturers to the IC designers. However, passing these complex DRC doesn’t autonomously guarantee a high IC yield, due to systematic defects that weren’t identified during the physical verification phase. Accordingly, in advanced manufacturing technology nodes, IC manufacturers require IC designs to comply with additional design-for-manufacturability (DFM) rules and checks to find and eliminate systematic defects and increase the design yield as much as possible. Line-end-pull-back (LEPB) is a well-known systematic defect in BEOL metal layers, where a line-end (LE) tip is pulled back from its desired location due to lithography (litho) process effects. Severe LEPB directly affects BEOL connectivity and may lead to partial or total metal-via disconnection. In this Thesis, we will focus on LEPB as a well-known contributor to systematic yield loss mechanisms.
This dissertation firstly introduces a novel edge-based approach named geometrical positioning surveying (GPS) that describes a LE as a point-of-interest (POI) and its surrounding context of patterns in the IC layout in a form of a feature-vector (FV) using directional geometrical kernels (DGKs). GPS provides a direct one-to-one mapping between features and physical geometrical measurements between the POI and its surrounding context of patterns, without the need to perform self-feature extraction steps. Moreover, it provides a direct POI-based analysis, rather than an image-based or density-based analysis, which are both time and computational resources-consuming.
The dissertation presents LEPB modeling using GPS features and regression-based machine learning (ML) approaches, specifically LightGBM regressor model. GPS provides a direct one-to-one mapping between input features passed to the ML model and physical geometrical measurements between the POI and its surrounding context of patterns, without the need to perform further self-feature extraction steps such as in deep-learning architectures. The obtained ML models provide a fast and accurate prediction of the amount of pull-back or extensions introduced at each LE with via and accordingly, identify the design locations particularly sensitive to systematic yield loss.
The dissertation uses GPS features to introduce an automated IC layout patterns topological profiling approach using DGKs to capture the context of patterns around a POI in an IC layout, such as a hotspot (HS). The DGKs are decomposed into topological and dimensional components. This makes patterns topological profiling mechanism doesn’t need complex models and can be precisely fine controlled to produce adequate patterns profiling granularity that is not easily approached by other patterns profiling alternatives.
This dissertation uses a fully connected industrial layout for a real design with electrical functionality and lithographic manufacturing recipes. We explain the employed manufacturing flow that used for simulations and data harvesting with a focus on BEOL interconnect layers stack. The collected data is used in IC layout patterns profiling and in LEPB modeling.