الفهرس 
ASIC Design of All Digital PLL’s for Processor-Clock Generation
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Abstract
All Digital PLLs (ADPLLs) are proposed as replacement for analog PLLs, thanks mainly to their scalability across technology nodes. This work presents a new standard-cell based ADPLL for processors{u2019} clock generation. The target technology is TSMC CMOS 130nm technology. The synthesized frequency ranges from 210 to 800 MHz. The total area of the ADPLL is 108*101om2. At 500MHz, The lock time, total power, rms jitter and peak jitter are 2os, 7.57mW, 2ps and 15ps respectively. These features make the proposed ADPLL design very suitable for SoC applications