الفهرس | Only 14 pages are availabe for public view |
Abstract This thesis presents a 24-44 GHz wideband highly linear and efficient class-AB 2-stacked power amplifier (PA) in 65-nm bulk CMOS process for 5G phased array applications. To boost the output power (POUT ) and power added efficiency (PAE) a differential 2-stacked transistor architecture with a higher supply (2V) is used. Cross-Coupled neutralization capacitors and shunt inductors are used at the intermediate nodes to improve the stability and PAE. In the proposed design, multiple techniques are used to achieve high efficiency and high linearity operation. First, an adaptive bias network (ABN), is used to adaptively control the bias of the PA to increase the gain at high powers (GP), POUT , and enhance the back-off PAE, especially in modulations with high peak to average power ratio (PAPR) (such as QAM). The second technique is adaptive RC feedback (AFB) which is used to improve the gain flatness versus power (AM-AM) by reducing the feedback as power increases. Lastly, an adaptive capacitive linearizer (ACL) is introduced to improve the (AM-PM) distortion. Transformer based matching techniques are used to obtain the wideband matching across the 24-44GHz band. The proposed PA achieves a Psat of 22.3 dBm, OP1db of 21.75 dBm with GP of 11 dB, and maximum PAE of 36%. The measured 6dB power back-off PAE is 26.9% and PAE at 9dB PBO is 19.5% at 24GHz. |