الفهرس 
Proposed opengl GPU architecture and implementation of line rasterization algorithm
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Abstract
The GPU has become an essential block for the embedded system devices. This thesis introduces a CUGPU, the Cairo University GPU, architecture based on the openGL ES 1.1 CL pro{uFB01}le. CUGPU supports the {uFB01}xed - function 3D graphics pipeline. Also, two designs of the line rasterization algorithm were implemented using VHDL code and synthesized at the TSMC 65 nm low power technology node. The {uFB01}rst design scores a typical clock frequency of 270 MHz and an area of 0.088 mm² . The second design scores a typical clock frequency of 200 MHz and an area of 0.052 mm²