الفهرس 
Frequency Synthesizers for Electrical Impedance Spectroscopy
Modeling of ?? ModulatorOnly 14 pages are availabe for public view
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Abstract
This thesis is introducing a modeling and circuit design for a direct digital frequency synthesizer for electrochemical impedance spectroscopy (EIS). EIS is a method used to measure the impedence of chemical material to differintiate between them as the impendence is changing with matrial type. The measurement is done by applying a sine wave signal at different frequencies on the sensor which is submerged in chemcial solution. Due to the impednce of matrial, the sensor output is having amplitude and phase shifts from the sine wave signal. By multiplying the sensor output and the applied sine wave through a quadrature mixer, the impedance of real and imaginary parts is extracted by demodulation of the signal to the baseband. If the sine wave signal has higher-order harmonics, the demodulation process will down-convert these harmonics to the base band. Hence, it distorts the measurement results. Therefore, the linearity of the sine wave is very important which is described by total harmonic distortion (THD). THD analysis is dependent on the type of sine wave generator circuit.
For DDS, it is a numerical control oscillator (NCO). It consists of a phase accumulator of N-bits, a truncator, and a lookup table (LUT) of L-bits. The LUT output is passed to a digital-to-analog converter (DAC) and filter to smooth the final output. Usually, the phase accumulator is determines the phase resolution of the sine wave. Its number of bits can be 15 to 20 bits. This number is very difficult to be used as an address for LUT which is a read-only memory (ROM). This ROM is storing the sine wave amplitude for different values of phases. Therefore, a truncator is used to truncate the N-bits to L-bits. This truncation is leading to loss phase resolution which leads to error in the output signal. Due to this truncation process and its repetition in every output clock cycle, spurs are generated at the output. Hence, it degrades the DDS THD. Therefore, a MATLAB model is used to simulate the effect of the N-bits and L-bits on the DDS THD. Moreover, it studies the filter order that is used at the output for smoothing and getting a better THD.
from the model, the output frequency ranges can be splitted in to two ranges, low frequency range and high frequency range. The required L-bits is 10-bits to all output frequencies. However, this solution needs to design a physical 10-bits DAC or more. However, from the model, a lower number of bits can be used to to support the high frequency range as the higher order harmonics of the signal can be filtered out by the output filter. Therefore, this thesis is introducing a re-configurable DAC. This DAC is working as a K-bits Sigma-Delta DAC for a certain range of frequencies depending on system specs and works as an n-bit DAC at a higher frequency range.
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For our system, it is required to support a frequency range from 1 kHz to 10 MHz. from the MATLAB model, the system clock is 25 MHz, the Sigma-Delta order is 3rd order, the filter order is 3rd order, the low-frequency range is starting from 1 kHz to 381.46 kHz, and the high-frequency range from 381.46 kHz to 10 MHz in the low-frequency range, the DAC is operating as 4-bits DAC while it is working as 8-bits DAC in the high-frequency range. The system is realized on 0.18 um CMOS technology, achieving a THD of less than 0.05% at low frequency and 0.08% at high-frequency range. The system is drawing a current of 1.3 mA from supply 1.8V.
The Thesis is divided into 6 chapters, the list of contents, tables, figures, and references