الفهرس 
Title : Low Power Nanometer FPGA Design Techniques at the Device and Circuit Levels
SummaryOnly 14 pages are availabe for public view
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Abstract
Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over last decades. The importance of FPGAs comes from their architecture, which consists of programmable logic functionality blocks and programmable interconnects. This nature of FPGA has a terrific impact on the quality of the final product{u2019}s performance, area, and power consumption. There are many techniques to make FPGAs more energy efficient. The different techniques can be categorized to: device, circuit, system, architecture, and computer-aided design (CAD). Device techniques refer to the usage of new emerging low-power process technologies offered by the semiconductor manufacturers, and new devices materials and structures. Circuit techniques refer to transistor level implementations of logic and routing resources. System techniques refer to high level techniques such as dynamic voltage and frequency control, power gating for unused resources, and dynamic reconfiguration. Architecture techniques refer to functionality of logic blocks, memory, and I/Os resources and the connectivity between these resources. Finally, CAD techniques refer to improvements added to the tools used to configure FPGAs to consider power consumption. In this work, we target introducing new design techniques to lower FPGAs power at device and circuit levels. First, we studied using dynamic threshold MOSFET (DTMOS) in FPGA logic blocks and showed that DTMOS can be used as a good candidate for designing ultra- low power FPGAs. The study also covered DTMOS MUXs as MUXs are the main part in FPGA routing fabricool which is widely used in academic researches of FPGA.