الفهرس Only 14 pages are availabe for public view
 |  | from | 118 |  |  |
| | | from | 118 | | |
Abstract
In this thesis, we evaluate various NoC design parameters to {uFB01}nd the best-{uFB01}t parameters that can be used in the noncon{uFB01}gurable hard NoC. We also evaluate di{uFB00}erent router architectures to select the optimum one for hard NoCs. The designed router reduces the wasted area by using minimum and shareable resources. Moreover, we propose an e{uFB03}cient novel way for embedding the hard NoC inside the FPGA. The proposed NoC provides the FPGA with a high performance communications infrastructure at a negligible cost