الفهرس 
Design of a reconfigurable network on chip for next generation fpga using dynamic partial reconfiguration
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Abstract
The main goal of this thesis is to present the runtime configurability support to CONNECT Network-on-Chip (NoC). Additionally, the thesis studies the reconfigurability impact on the network performance with its different configuration parameters. In comparison with the fixed NoCs, the runtime configurable NoCs save area by reusing a part of the network when it is not required during runtime. A reconfiguration tool is developed helping the user to decide the optimum network structure for every used benchmark