الفهرس 
Power-efficient design of high performance googlenet-based convolutional neural networks hardware accelerator
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Abstract
Convolutional neural networks (CNNs) have dominated image recognition and object detection models in the last few years. However, they require a huge cost of computation and a large memory size.This thesis presents a low-power convolutional neural networks hardware accelerator based on GoogLeNet.Several optimization and approximation techniques are applied to reduce the power consumption and memory size.Consequently, only FPGA BRAMs are used for weights storage without using offline DRAMs. In addition, the proposed hardware accelerator uses zero DSP units.The accelerator classifies 25.1 frames/sec with only 3.92W, which is more power-efficient than previous GoogLeNet FPGA implementations.The processor uses only 224 parallel elements (PEs) and achieves an average classification efficiency of 91%