الفهرس 
IntroductionOnly 14 pages are availabe for public view
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Abstract
Due to its low resistivity and the ease with which it can be electrodeposited, copper has been used for fabrication of on-chip interconnect wiring in the semiconductor industry since the late 90s(1). Copper electrodeposition remains the dominant technology for interconnects on microelectronic devices over many scales from interposers with line widths on the micron scale to nodes a few tens of nanometers in size. The interconnects are fabricated by electrodeposition of copper into trenches to produce lines, or into holes to produce vertical interconnects. The major challenge for the success of the process is to fill the features completely without leaving seams or voids. This in turn requires rigorous control over the distribution of plating current inside the features, a problem that becomes more difficult as the feature size is reduced.