الفهرس 
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Abstract
Photonic networks and software-defined networks are two emerging innovations that have a prominent impact on the improved performance, scalability, and resource utilization of network-on-chips while several existing architectures suffer from scalability limitations, high-power consumption, noise and interference drawbacks. In this thesis, an enhanced photonic network-on-chip architecture called SD-PNoC is presented. The proposed architecture is based on a hybrid hardware-software approach, in which a Software-Defined Management Orchestrator (SDMO) is introduced to separate the network control and data forwarding planes. The proposed orchestrator is hosted on the top of the upper hardware router as a virtual layer that is capable of performing dynamic management. The proposed orchestrator provides dynamic reconfiguration for the data forwarding paths to allow concurrent and dynamic execution of different algorithms in real time, as it reconfigures the on-chip network topology based on the type of application and network efficiency and processing elements utilization. The proposed SD-PNoC architecture, hierarchical communication protocols, and the orchestrator policies were implemented, simulated, and tested using a customized Phoenix-SIM framework in the OMNIT++ simulation environment. Numerous simulation experiments under different conditions have been conducted to verify, validate and evaluate the performance of the proposed solution and to compare its results with the existing network-on-chip (NoC) architectures. Many experiments have been conducted to test each module separately, as well as the integrated system. Two experiments categories were identified for the final testing, namely; experiments by using SDN alone, and experiments by integrating SDN and the orchestrator. Simulation results without using the management policies showed that the latency is reduced by 46% and 25.5% for the 4x4 and 8x8 mesh network structures, respectively. Meanwhile, the power consumption is reduced by 76.5% and 78.5% for the 4x4 and 8x8 mesh network structures, respectively. Additionally, the chip area is reduced by 33.4%. Moreover, the simulation results after integrating the Software-defined Management Orchestrator (SDMO) for the 8x8 mesh network structures, improved the latency from 25.5% to 37.3% and the power consumption from 78.5% to approximately 80%, which assure the ability of the proposed architecture to enhance the overall performance of complex network-on-chip structures.