الفهرس 
Contributions
System design owOnly 14 pages are availabe for public view
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Abstract
In the recent years, the system on a chip (SoC) design has seen many advances due to the new technology nodes and the increase of system complexity. All-digital phase locked loop (ADPLL) usage gained more consideration in the advanced nodes SoCs, the building blocks of the ADPLL are mostly digital blocks, which gives it upper hand over the analog phase locked loop due to the easiness of integration, scalability with the technology nodes, flexibility of design and operation of the digital blocks, and immunity to supply noise and variations.
This thesis presents a design and optimization tool for the ADPLL system and circuits. The tool is implemented using Matlab scripts that create optimized design netlists and runs circuit simulator to simulate these netlists and verify the system requirements.
The thesis is divided into six chapters as listed below:
Chapter 1 This chapter is the introduction of the thesis. It starts with an introduction to the PLLs and ADPLL. Then the contributions of this thesis. Finally presenting the thesis organization.
Chapter 2 This chapter starts with literature review of the ADPLL system models, then discusses the used model and the tool’s flow and the contributions to this model to determine the system parameters.
Chapter 3 In this chapter, the DCO architectures are discussed, and the automated design flow using gm/ID methodology is presented. also the design flow of the capacitor banks is presented.
Chapter 4 In this chapter, the automated digital design flow for the digital blocks is presented. Starting from the circuits specifications, till the automatic synthesis, placement and routing of the circuits’ RTL
Chapter 5 In this chapter design examples are implemented using the design tool. The system simulations are presented and the results are discussed.
Chapter 6 The conclusion of the thesis is given in this chapter, in addition to suggestions for future work.