الفهرس 
CHAPTER 1 1 INTRODUCTIONOnly 14 pages are availabe for public view
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Abstract
Physical Unclonable Functions (PUFs) are promising hardware security primitives that are based on the uniqueness and the unclonability of the device’s physical characteristics to provide a unique identifier for devices. PUFs are suitable for low power applications, such as the Internet of Thing (IoT). PUFs can be used in device authentication and for secure key storage and generation. The Ring Oscillator (RO) PUF is one of the most reliable and strong PUFs. On the other hand, it consumes more power than others. The main aim of this thesis is to propose a design for a low power PUF. In this thesis we propose three new PUFs architectures, which are suitable for low power applications. The three proposed PUFs were designed using 20 nm triple gate FinFET technology.
The first proposed design presents a Frequency Divider Ring Oscillator PUF (FDRO-PUF). The FDRO-PUF design is based on utilizing modules that consume less power than the conventional one. In the FDRO-PUF design the Frequency Divider (FD) and the D-flipflop (DFF) are employed instead of the counters, the timer, and the comparator circuits. Evaluation results demonstrate that the FDRO-PUF design can effectively reduce power consumption. The FDRO-PUF consumes 264 μW per challenge-response pair at supply voltage 0.9 V. The averaged reliability of the proposed design is 99.5 %, over a range of temperature from -40 to 125 ◦C and supply voltage from 0.8 V to 1 V.
The second proposed design presents Edge Detector Ring Oscillator PUF (EDRO-PUF). The EDRO-PUF design is based on biasing the ROs near the threshold voltage to reduce the consumption power. In the EDRO-PUF design the FD and the Edge Detector (ED) replaced the counters, the timer, and the comparator circuits. Simulation results demonstrate that the EDRO-PUF design can effectively reduce power consumption. The Simulation results for 1000 different chips with the same input challenge, show that the average power is 2.2 μW, at supply voltage 0.5 V. The average reliability of the EDRO-PUF is 99.1%, at temperatures from -40 to 125 ◦C and supply voltage 0.5 ± 10%.
The third proposed design presents Oscillator Collapse Physical Unclonable Function (OC-PUF). The power consumption is reduced based on designing the most power-hungry modules in the OC-PUF. An Oscillator Collapse (OC) is designed to work in the near-threshold voltage region reducing power consumption. More power reduction is achieved by designing a new Collapse Time Comparator (CTC). Due to the process variations, the oscillation period of each OC is different. The CTC generates the output response bit by comparing the oscillation periods of the two selected OCs. The simulation results demonstrate that the proposed OC-PUF can effectively reduce the power consumption. The Simulation results for 1000 different chips with the same input challenge, show that the average power is 140 nW, with the worst case being 740 nW. The best case is 63 nW per challenge-response pair at supply voltage 0.5 V. The average reliability of the OC-PUF is 99.8%, at temperatures from -40 to 125 ◦C and supply voltage 0.5 ± 10%. The three proposed PUFs decrease the power consumption while retaining high-performance metrics.