الفهرس 
الغلافOnly 14 pages are availabe for public view
 |  | from | 150 |  |  |
| | | from | 150 | | |
Abstract
Power consumption and area of VLSI systems are the main issues in the electronics industry, which triggered many research efforts to minimize the power consumption and area of VLSI circuits, while battery technology doesn’t advance at the same rate as the microelectronics technology, There is only a limited amount of power available for portable electronic devices heavily used on a daily basis.
Gate Diffusion Input Technique (GDI) is gaining popularity due to its reduced transistor count, power consumption and delay compared to CMOS and other logic styles. The efficiency of the GDI technique for both combinatorial and sequential logic was reported by many groups.
Arithmetic Logic Unit (ALU) is an essential building block in many applications such as microprocessors, DSP, and image processing. As the ALU is one of the most power-hungry components in the processor, therefore, low power design of ALU can reduce the total power consumption of a processor.
This work presents a 4-Bit ALU designed in 65nm CMOS processes using the full-swing GDI technique and simulated using the Cadence Virtuoso simulator. Two designs of the ALU are presented.
Design 1: results showed the advantages of the proposed ALU design in comparison with conventional CMOS design in terms of power consumption, propagation delay, and transistor count while maintaining full-swing operation. Hence the energy of the 4-bit ALU reduced by 32% compared to CMOS based design. Design 2 consists of 286 transistors.
In design 2: delay time of the 4-Bit ALU reduced by 22.3% compared to the design 1, while maintaining full-swing operation. Hence the energy of the 4-bit ALU reduced by 21.2%. Design 2 consists of 294 transistors; both designs operate under 1.2V supply voltage and frequency of 125 MHz