الفهرس 
Mathematical BackgroundOnly 14 pages are availabe for public view
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Abstract
The area and power optimizations with cryptography are two important design issues for embedded processors and constraint devices, at the design level, targeted to lightweight, handheld, and IoT (Internet of Things) applications. One benefit of elliptic curve cryptosystems (ECCs) is that they can be developed using a much shorter key length than other public key crypto-systems to provide an equivalent level of security, in addition to, short signature. However, hardware implementation of Elliptic Curve Crypto-Processor (ECCP) for lightweight devices is a challenge in order to meet the requirements of lower power consumption, shorter bandwidths, higher speed, fewer registers in the Register File (RF). This dissertation aims to propose a high performance processor for elliptic curve cryptography (ECC) over ( )and ( ) by using polynomial presentation.
The objective is to develop and implement a near optimal ECCP based on the Field Programmable Gate Array (FPGA) hardware design. The challenge is to implement the main operation of Point Multiplication (PM) ( ) using FPGA. The goal is to obtain the optimal registers number for an area optimization of ECCP architecture; furthermore, it proposes a time optimization of ECCP based on the liveness analysis and exploiting forward paths. ECCP is a multi-level architecture model. The contributions showed the performance of the curve by highlighting the effect of both parallel and serial work at all levels of the ECCP. A finite field polynomial multiplier takes the most implementation effort of an ECCP because it is the most consuming operation for time and area. The formulas that used to implement the inversion operation in finite field are explained and implemented in which the inversion operation based on Itoh-Tsujii is discussed in this work. This work involved the development of a new Itoh-Tsujii inversion algorithm for finite field ( ). Comparisons with state-of-the-art algorithms that have been used to implement ECCP are also presented. It proves that Montgomery ladder algorithm is preferred one when the speed is needed.
The developed ECCP design is implemented over Galois Fields ( )and ( ) on Xilinx Integrated Synthesizes Environment (ISE) Virtex 6 FPGA. In case of ( ), this work achieved an area saving that uses 2083 Flip Flops (FFs), 40876 Lookup Tables (LUTs) and 19824 occupied slices. The execution time is 1.963 μs runs at a frequency of 369.529 MHz and consumes 5237.00 mW. In case of ( ), this work achieved an area saving that uses 8129 Flip Flops (FFs), 42300 Lookup Tables (LUTs) and 18807 occupied slices. The execution time is 29 μs runs at a frequency of 253.770 MHz and consumes 2W. The obtained results are highly comparable with other state-of-the-art crypto-processor designs. The developed ECCP is applied as a case study of a cryptography protocol in ATMs.