الفهرس 
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Abstract
In many Digital Signal Processing (DSP) applications performance
is recognized as one of the significant parameters in designing the digital
system. The performance of DSP processors is mostly reliant on the Multiplier and Accumulator (MAC) unit. The computing efficiency of these applications rely on the speed/of the adders and multipliers used in the MAC unit. The speed can be increased by using high speed adders and multipliers. In the past, main focus has been on the circuit speed.
However, currently, low power requirement in these circuits has become
more imperative.
MAC is now utilized in different DSP applications, distributed
computing applications and processors in its ALU unit. So, by enhancing
the MAC unit, we could improve the performance of the digital signal
processors.
So this research presents high speed and low power 4-bit MAC
circuit in VLSI. Three designs of low power I-bit full adder proposed,
which using 1ST, 16T and 18T based on full swing GDI technique. MAC
designed by using a different architecture of multipliers like Array,
Barun, Wallace and Baugh Wooley multiplier and compared with the
conventional architecture through cadence virtuoso simulation based on
TSMC 65 nm models at a supply voltage of 1.2v and frequency 29MHz.
The simulation results showed that the proposed MAC design dissipates
low power while improving the area and provides a full swing output
voltage as compared to conventional MAC.