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العنوان
Design of Wireless Transceiver Front-end \
المؤلف
Zamzam,Ahmed Mohamed Attia
هيئة الاعداد
باحث / أحمد محمد عطية زمزم
مشرف / هانى فكرى رجائى
مشرف / محمد أحمد محمد النزهى
مناقش / السيد مصطفى سعد
تاريخ النشر
2018
عدد الصفحات
133p.:
اللغة
الإنجليزية
الدرجة
ماجستير
التخصص
الهندسة الكهربائية والالكترونية
تاريخ الإجازة
1/1/2018
مكان الإجازة
جامعة عين شمس - كلية الهندسة - قسم الالكترونيات والاتصالات
الفهرس
Only 14 pages are availabe for public view

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Abstract

There is a huge demand for fully integrated, small size, and highly efficient transceivers, due to the enormous growth of wireless applications. Power amplifier (PA), specifically determines the performance of these transceivers, as it is the most power hungry block. Hence, any enhancement in its efficiency would result in a great decrease in the total power consumption. This thesis aims to study the technology performance limits as well as the design challenges of PAs. Due to the fact that the transceivers need to not only support high data rates but also have small cost, the main focus is on the commercial low cost CMOS technologies. Different active and passive loss mechanisms have been studied, and a new cascode switching technique has been proposed to increase the efficiency at 15 GHz. The proposed technique results in an enhancement of PAE by about 10.6 %.
In the recent years, a huge attention has been drawn to millimetre frequency range. This can be explained by the huge bandwidth allocated in these bands, which can result in very high data rates. In addition, the high frequency design enables the implementation of small size and high quality passives, which helps in achieving low cost, small form factor transceivers. 60 GHz offers an additional advantage, which is the reduced coverage range, and this provides better security. A state of the art ON/OFF key (OOK) 60 GHz transceiver architecture has been proposed. This architecture enables delivering high output power and low noise figure. In addition, a 60 GHz transmitter has been designed in bulk 65nm CMOS process. The transmitter utilizes a new current combined stacked injection locking topology which enhances both output power and efficiency. This PA delivers 19.5dBm output power with 15.5 % PAE.
The transmitter occupies an area of 1.5mmx1.2mm. Modelling of all the implemented inductors, capacitors as well as the layout routings is carried out using the electromagnetic simulator, SONNET. Post layout simulations show that the transmitter can deliver 20dBm output power with 10 % efficiency.