الفهرس 
Power characterization
Transaction Level Power Modeling MethodologyOnly 14 pages are availabe for public view
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Abstract
The advance in processing technologies has derived the complexity of electronic design. Building System-on-Chip (SoC) platforms are af- fected dramatically with respect to the product life cycle. The shrink- age of the transistor length creates sophisticated design models. Thus, the simulation time for those models is getting longer, so it takes weeks for simulation of one module in the platform. Electronic design automa- tion (EDA) companies and research institutes have been developing CAD tools and flows to contentiously support building new SoCs. This is achieved through creating new modeling techniques to keep the design life cycle short in the industry. One of these techniques is Transaction Level Modeling (TLM) using SystemC. TLM introduces abstract mod- eling of communication scheme between design modules. Power con- sumption is a key specification in any design. Determining the power of large SoC designs is very computational and time expensive on Register Transfer Level (RTL), if even possible.
This thesis presents a methodology for dynamic power estimation us- ing TLM. The methodology exploits the existing tools for RTL simula- tion, design synthesis and SystemC prototyping to provide fast and accu- rate power estimation using Transaction Level Power Modeling (TLPM).
Evaluating power consumption at early phase of product life cycle is im- portant to decrease the number of the expensive design iterations. Com- mercial IP timer is used to validate and evaluate the proposed method- ology. Different scenarios are exercised to cover the functionality of the timer. Finally, experimental results show the accuracy and efficiency of the methodology as compared to RTL.