الفهرس 
Data Converters: Specifications andOnly 14 pages are availabe for public view
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Abstract
The realization of wireless sensor networks (WSN) put stringent requirements on its different building blocks. Among different blocks, the analog-to-digital converter (ADC) design proves to affect the overall system performance, especially in systems employing complex digital signal processing (DSP) algorithms. Static offset, clock jitter, signal-to-noise ratio (SNR), and system linearity are examples of different system specifications that directly impact the ADC design. In this thesis, the main focus is the design of an ADC for WSN application, implemented in CMOS technology.
The thesis is divided into six chapters including lists of contents, tables and figures as well as list of references and the appendices.
Chapter 1
Chapter 1 introduces the main motivations beyond digital domain processing and the driving factors. A brief outline of various ADC applications is presented with major focus on wireless sensor networks harassed for bio-medical applications such as ECG signals monitoring. The chapter ends by clearly identifying the main challenges imposed on ADC design in such systems regarding power and area requirements, clearly identifying the proper context of this work.
Chapter 2
Chapter 2 aims to provide a quick refresher in regard of the basic ADC systems and the encountered signal processing steps. It goes further with brief discussions clarifying the main performance metrics and terminologies used in the world of ADCs. The rest of the chapter is devoted to a quick literature review on the basic ADC architectures, their main operation principles, non-idealities, and recent innovations and state-of-the art architectures.
Chapter 3
Chapter 3 starts by briefly recapping the main challenges obviating SAR and Sigma-Delta ADCs from achieving high power efficiencies at high resolutions. The theory of feed forward noise shaping (FFNS) is proposed, generally as a new ADC architecture in which the noise shaping is achieved without placing the main quantizer in a feedback loop, and specifically, as a hybrid solution that merges the high power efficiency of SAR ADCs with the high resolution capabilities of noise shaping, along with benefiting from the basic idea of digital error correction incorporated in pipelined ADCs.
Behavioral system models have been developed along with the appropriate quantitative analyses to support the proposed idea. System block diagrams for first and second order FFNS based ADCs have been extracted and generalized to Lth-order FFNS architectures. Finally, the theory of FFNS has been extended to build up partially oversampled FFNS-based ADCs.
Chapter 4
Chapter 4 deals with the design considerations of the proposed FFNS-based system. SAR ADCs have been chosen as core quantizers owing to their high power efficiencies. The chapter starts by revisiting the bio-medical application under question, and conducting a power budget for a given set of specifications. A quantitative comparison between the Conventional Binary Weighted (CBW) and Binary Weighted DAC with Attenuating capacitor (BWA) switching schemes have been conducted showing that the former is more superior to the latter, in terms of area and power consumption, when linearity requirements are taken into account.
The chapter proceeds, afterwards, by conducting a quantitative power driven model for the proposed FFNS system.
Chapter 5
Chapter 5 presents the design details of 1st order FFNS and PO-FFNS based ADCs. For each system, a proposed circuit implementation is proposed along with carefully analyzing non-idealities effects. Detailed design of all sub – blocks is presented along with overall system simulations.
Chapter 6 presents a summary for the dissertation, along with possible directions for future work.