الفهرس 
INTRODUCTIONOnly 14 pages are availabe for public view
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Abstract
Clock Multipliers are widely used in all digital systems, there is different architectures used to generate this clock, the need to minimize jitter in this clock is a must, there is techniques to minimize jitter .In this dissertation one of this techniques were used.
This dissertation starts with a survey on different architecture used as a clock multiplier then it concentrates on multiplying DLL architecture, a survey on previously implemented MDLL was made.
Next in this dissertation is the linear model of the multiplying DLL and it was used to extract loop parameters and to predict the total phase noise and in consequence the jitter .Linear model was assuming the loop to work as a PLL or DLL.
Next, the dissertation presents the implementation of a complete time domain model of the MDLL and from this model, different block requirements were extracted .The linear model was implemented using VerilogA language .
Next , the circuit implementation was made for all blocks in the MDLL , each block was designed and simulated and verified in the system , and at the end a verification of the whole system was made in the MDLL mode and PLL mode .All circuit implementation was done using 0.13um technology node .Simulation was done using Spectre