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العنوان
Network on chip energy-Aware architecture /
المؤلف
Youssef, Ahmed Mahmoud Mostafa.
هيئة الاعداد
باحث / أحمد محمود مصطفى يوسف
مشرف / مدحت حسين أحمد
مشرف / السيد مصطفى سعد
مشرف / سامح عبد الرحمن سالم
الموضوع
Networks on a chip. Autonomic computing.
تاريخ النشر
2012.
عدد الصفحات
p i-xv ,165. :
اللغة
الإنجليزية
الدرجة
الدكتوراه
التخصص
الهندسة الكهربائية والالكترونية
تاريخ الإجازة
1/1/2012
مكان الإجازة
جامعة حلوان - كلية الفنون التطبيقية - هندسة الالكترونيات
الفهرس
Only 14 pages are availabe for public view

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from 197

Abstract

As technology moves towards multi-core system-on-chips (SoCs), networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. One of the most trade-off aspects in the design of NoCs is the improvement of the network performance, in terms of throughput and latency, while minimizing power consumption.
In this thesis, the system power consumption of the global interconnection links in NoC-based systems is analyzed. Based on this analysis, a new optimization algorithm to find the network topology and the processing elements (PEs) mapping that matches the traffic characteristics of the NoC-based application and gives the lowest power consumption on the global interconnection links is proposed. The robustness and reliability of the proposed algorithm is verified in the context of Moving Picture Experts Group (MPEG4) video application. The achieved experimental results show that the proposed optimization algorithm find the optimum mapping of large number of tasks with much less time compared with the exhaustive search algorithm.
,
A performance and power network on chip simulator (PPNOCS) has been
proposed. PPNOCS is based on SystemC and explores the impact of various architectural level parameters of the on-chip interconnection network on its performance and power. PPNOCS supports an arbitrary size of mesh and torus topology, adopts five classic routing algorithms and seven synthetic traffic patterns. Experiments of using this simulator are carried out to study the power, latency and throughput of a 4 x 4 multi-core mesh network topology. Results show that PPNOCS provides a fast and convenient platform for researching and verification of NoC architectures and routing algorithms.
As 2D-mesh has become the preferred topology, since it offers low and constant link delay. A Power efficient, Oblivious, Path-diverse, Minimal routing (POPM) for mesh-based Networks-on-Chip has been proposed. In order to improve the performance of the network, POPM makes routing decisions locally at each hop rather than establishing a fixed and deterministic path between the source and destination nodes. POPM routes each packet separately through a path selected from among all minimal paths. Detailed simulations on a set of synthetic traffic patterns as well as a real application traffic pattern show that POPM competes favorably to existing routing algorithms, including dimension-ordered (DOR) routing, North-Last routing, and Path-based, Randomized, Oblivious, Minimal (PROM) routing.
Finally, an integration of the proposed mapping technique and the POPM routing algorithm is developed to analyze the impact of their joint application on the network performance and power consumption. The proposed technique is verified through four different video processing applications: Moving Picture Experts Group (MPEG4), Video Object Plane Decoder (VOPD), Multi-Window Display (MWD), and Picture-In¬Picture (PIP). The evaluation results show that the proposed integrated technique significantly improves network performance and power consumption.