الفهرس 
ADPLL BasicsOnly 14 pages are availabe for public view
 |  | from | 154 |  |  |
| | | from | 154 | | |
Abstract
The thesis contains a study for some Digital Techniques in Frequency Synthesis
that makes the use of an All Digital PLL possible. At the heart of the All Digital PLL lies a
Digitally Controlled Oscillator which deliberately avoids any analog tuning voltage
controls. We address two of the main issues of the Digitally Controlled Oscillator; that is
its center frequency (fDCO)variations & tuning gain (Koco) variations.
To mitigate the center frequency variations, we propose a new fast automatic
tuning algorithm for LC based oscillators. The proposed algorithm is verified over a wide
range of initial Digitally Controlled Oscillator frequencies & phases to guarantee robust
operation over all process corner variations with the worst case tuning time being only
7.2Ilsec.
To mitigate tuning gain variations, we study a fast tuning gain estimation &
calibration algorithm. This tuning gain calibration makes it possible to lise a two point
modulation scheme to transmit Frequency Shift Keying data at symbol rates much
higher than the loop bandwidth upto the Nyquist frequency of half the reference
frequency.
We use a Verilog model to verify the successful All Digital PLL functionality &
performance transitioning from reset to center frequency automatic tuning to tuning gain estimation & calibration to Frequency Shift Keying data transmission. Also when
used as a local oscillator. the implemented All Digital PLL has spurious tones at only
·98dBc.