الفهرس يوجد فقط 14 صفحة متاحة للعرض العام
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المستخلص
—<In the past decade processors were improved by using vector instructions called SIMD instructions. Those vector instructions have dramatically enhanced the performance of many multimedia applications.This thesis studies a code selection technique capable of generating SIMD instructions automatically in the context of dynamic compilation. This technique develops a portable implementation using loop unrolling and tree pattern matching techniques. The proposed implementation is applied on the optimized compiler of Jikes RVM in the phase of converting Lower Intermediate Representation code into Machine specific Intermediate Representation using the benefits of BURS system. The current work proposes a new BURS rules capable of generating SIMD instructions that perform a manipulation (arithmetic or logic operation, load or store) of data stored in subregisters instead of full registers. In addition, it proposes a technique capable of checking the constraints required to guarantee the validity of packing each pair of operation into one SIMD instruction.
Applying the suggested implementation in Jikes RVM with IA-32 architecture results an overall speedup at runtime despite the runtime overhead of the compilation phase.