الفهرس 
RF Frequency SynthesizersOnly 14 pages are availabe for public view
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Abstract
The thesis is an attempt to study the different aspects of the design of an RF
phase-locked loop (PLL) frequency synthesizer (FS) for use in wireless
transceivers. Starting from the wireless standard requirements to the transistor
implementation of the FS involves three main phases: system level design of the
PLL, transistor level design of the building blocks and system integration and
verification. An RF PLL FS is rich in circuit design and verification challenges
since it is typically composed of RF, high-speed digital, analog, and mixedsignal
interacting blocks. Time-efficient design of a complete PLL frequency
synthesizer requires good knowledge of the impact of block implementation
non-idealities on the system performance with a preferab!~ coupling of the three
design phases. A top-down design methodology ana bottom-up verification are
adopted. These approaches are based on heavy use of behavioral models written
in a mixed-signal hardware description language. A frequency synthesizer
meeting the DECT cordless telephone standard has been used throughout the
study.
The system level design of the integer-N PLL FS was successfully done with
the help of Veri log-A models describing the PLL in the s-domain. The models
facilitated the analysis of the system stability and dynamic performance as well
as simulating the closed loop synthesizer phase noise. The majority of the transistor level design has been done using a O.81lm 5V CMOS process. A new
D-Iatch has been proposed’ that is competitive with current implementations in
terms of speed and power. The D-Iatch was used to design a divide-by 32/33
dual-modulus prescaler working at 1.7GHz and dissipating 20mW. The proposed latch circuit was slightly modified and used as a voltage controlled
delay cell in a novel single-stage ring oscillator. The voltage-controlled
oscillator has a phase noise of -112dBclHz at an offset of 3.456MHz from a
1.6GHz carrier and dissipates 40mW. A current-steering charge-pump was
analyzed in terms of static current mismatch and output noise. The analysis
resulted in a systematic design procedure for high performance charge-pumps
and was used in designing a charge-pump with a maximum pumping current of
200~ and a 5% static current mismatch. A phase/frequency detector (PFD)
was also designed using the proposed D-latch. The complete system was
integrated on the transistor level with the exception of the programmable
counters of the pulse-swallow counter. Verification of the system was done
using an incremental incorporation of the transistor level designs with the help
of specially developed elaborate behavioral models written in Verilog-A using a
bottom-up verification approach. The verification process helped understand
and quantify the effect of each block on the FS performance thus opened a lot of
issues that may be studied in the future.